Simulação em VHDL de máquinas de estados finitas hierárquicas

Abstract

This paper discusses the VHDL simulation of Hierarchical Finite State Machines. It presentes the results
obtained with the simulation of the model described in [1], introduces a new model and shows its advantages. Both Moore and Mealy machines are being considered. The considered model provides such new facilities as flexibility, extensibility and reuse of an algorithm described by Hierarchical Graph-Schemes.