Geração de vectores de teste por emparelhamento

Abstract

This paper presents a method to generate test vectors for an electronic board composed of modules from which the structural description it’s not known. The only information available is the set of test vectors, their coverage on the primary inputs and outputs of each module provided by the manufacturer and the composition of the board. This method provides test vectors to test the board from its primary inputs and outputs and was automatized, resulting in a iterative software tool, developed in C language.