Realização em tecnologia monolítica de arsenieto de gálio (GaAs MMIC) de amplificadores sintonizados para recuperação de relógio a 10 e 20 Gbps

Abstract

Nowadays the clock recovery circuits used for frequencies up to 10 Gbit/s use open-loop structures. The band-pass filters used on these structures are implemented with dielectric resonators (DR). This kind of filters introduce spurious modes that degradate the characteristics of the recovered clock signal. So, the clock amplification stage is required not only to provide the desired clock signal levels, but also to reduce the magnitude of the DR filter spurious modes. Next is presented the project, simulation and design of two amplifiers (GaAs MMIC) operating at 10 and 20 Gbit/s, to be integrated in a clock recovery circuit.