Extractor de relógio versátil

Abstract

Digital transmission systems have an increasing importance in communications. It is essencial a good clock recovery system for the proper operation of these systems. In this work, a clock extraction circuit has been implemented in an ASIC, requiring only a very reduced number of external components. This is specially oriented towards laboratory applications, and is projected to acquire synchronism with a wide range of bit-rates (1 to 20 Mbps) and several line codes.