Synthesis and simulation of reprogrammable control units from hierarchical specifications

Authors

  • António Manuel Adrego da Rocha
  • Valery Sklyarov Orientador
  • António Ferrari Orientador

Keywords:

Finite state machines, Hierarchical specification of control units, Logic synthesis, VHDL simulation

Abstract

Finite state machines (FSM) have been a topic of great importance in the last five decades and have been used ti specify and implement control units. Due to the increasing complexity of control units and since the FSM model does not explicitly support hierarchy and concurrency, new state-based models with hieararchical and concurrent constructions were proposed in order to overcome the limitations of conventional FSM model and allowing the specification of complex control units in a top-down manner. (...)

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Published

2000-01-01

Issue

Section

Doctoral thesis: abstract