Specification, Optimization and Testing of Hierarchical Control Algorithms

Abstract

This work is devoted to the specification of control algorithms, their verification, optimisation, conversion to VHDL (VHSIC Hardware Description Language) code and real-time debugging. The behaviour of control algorithms is described by HGSs (Hierarchical Graph Schemes), which is a formal graphical specification language similar to flow charts. This method supports hierarchy and parallelism and allows building control algorithms using a notation that is independent of the circuit implementation model. Within the scope of this work, a software tool, called GraphBuilder, was developed. It consists of an integrated environment for specification, experimentation and test of hierarchical specifications. (...)