A coprocessor for traffic scheduling and schedulability analysis in FTT-CAN

Abstract

The low-processing power microcontrollers typically used within CAN nodes, usually place tight limits on the complexity and flexibility of on-line message scheduling systems. One solution to break this barrier is to transfer the scheduling task to a hardware implementation. A preliminary version of a traffic scheduling and schedulability analyser coprocessor is proposed in this paper. This coprocessor, which will be implemented on a low-cost FPGA, can generate message schedules for the node CPU, leaving it just with the dispatching task. Adding to this, scheduling can be made to follow one of three different policies, and the number of messages to be scheduled and their respective parameters can be changed dynamically. To support on-line admission control of new messages, the coprocessor implements a schedulability analyser function. The coprocessor was designed to support the FTT-CAN protocol, but it can be adapted to any other fieldbus using centralized scheduling. Since the coprocessor is still in an early design stage, nomeasures of performance are yet available.