CLAN: a CAN 2.0B protocol controller for research purposes

Abstract

The CLAN intellectual property core is a CAN 2.0b controller developed at the Electronics and Telecommunications Department of the University of Aveiro, for research and educational purposes and in particular with the aim of providing the adequate hardware support to implement and validate higher layer protocols such as TTCAN or FTT- CAN. It was modelled at RTL level using the VHDL hardware description language, synthesized, implemented and tested on Xilinx FPGAs. However, the model is technology independent and can be synthesized for different implementation technologies from FPGAs to ASICs. The CLAN IP core fully implements the CAN 2.0B spacification and it includes also a syncronous parallel microprocessor interface, interrupt generation logic and some advanced features, such as message filtering, single shot transmission and extended error and statistics logs. The data bus width can be 8, 16 or 32 bits wide. For aplications where a microprocessor interface is not needed or a different interface is required, the core internal module that implaments the protocol can be used separately. CLAN controller with microprocessor interface logic occupies about 30% of a Xilins Spartan-UE XC2S300E FPGA, corresponding to 100.000 equivalent logic gates, approximately. It was tested with other CAN controllers operating at 1Mbit/seg.