Sudoku em FPGA

Abstract

This paper describes the implementation ofaSudoku solver, developed in the context of reconfigurable systems. Thus, three solvers were developed: Simple, only able to solve simple puzzles, Trial and Error, whichimplements a Breadth-First Search algorithm, being able to solve more complex puzzles, and, finally, Trial and Error solver with the possibility of parallel processing. For theimplementation and test an FPGA of the Xilinx Spartan-3E family was used, using for the purpose a prototyping board from Digilent. The results were compared between the threeimplementations as well as with other state-of-the-art solvers. The project was developed within the Master Thesis “Sudoku em FPGA”.