Design and characterization of a 20 Gbit/s clock recovery circuit

Abstract

In this communication we report the design of a clock recovery circuit produced for the 20 Gbit/s demonstrator of the RACE 2011 project "TRAVEL" of the European Community. The clock recovery circuit is based on an open loop structure using a dielectric resonator narrow bandpass filter with high Q. A detailed electrical characterization of the circuit and alsoits sensitivity to temperature and detuning variations arepresented. The experimental results show that the circuit is avery attractive solution for the forthcoming STM-128 opticallinks.