Design of a communication and shared memory management unit

Abstract

In this paper we present an overview of the architecture, the design process and the main properties of a communication and shared memory management unit for a MIMD type multiprocessor mesh. The circuit has been completely specified and was later designed as a standard cell ASIC based on ES21 ECPD10 library of cells, for a N-Well CMOS m process. The CAD framework used was Cadence Edge (ES2 SOLO 203