Using high-level languages for hardware modeling and implementation

Abstract

This paper describes the use of highilevel languages in hardware modeling and implementation. The purpose of the article is to describe a methodology that can be used in the design of anew system. First we will describe the main phases of hardware design flow, namely: modeling, validation, synthesis, implementation, prototyping and testing. We will also give a brief overview of somehigh-level languages. Afterwards, we will propose a methodology, where a new system is designedusing successively a subset of C++. SystemC and VHDL using some guidelines to provide a smooth transition between languages and levels of abstraction. We will present a case study where an UART has been designed using this methodology. We will report the advantages and disadvantages of eachlanguage. This methodology provided a clear refinement flow from a functional sequential modelto a RTL synthesizable model, although it created some consistency problems. The UART was implemented together with a MIPS32 processor within a FPGA for prototyping and testing purposes.