Especificação, síntese e implementação em VHDL de um processador MIPS Single Cycle Simplificado

Abstract

This paper describes an implementation of reconfigurable circuits which emulate an instruction subset of a simplified MIPS RISC Single Cycle processor. The MIPS processor can be decomposed in five functional stages: Instruction Fetch, Instruction Decode, Execution, Data Memory, and Write Back. The Control Unit operates in all of these stages, managing the way each operation should be executed. All the components of the architecture were specified using VHDL, allowing to establish the parallelism between behavioral hardware description and circuit implementation. Different simulation scenarios were created to analyze the functionality of the designed system, execution times and performance. In the near future, a graphical interface is going to be developed, making it possible to visualize the values of the processor’s signals in real time. The designed project can be successfully employed withinReconfigurable Computing (4th year of ComputerEngineering curriculum), Reconfigurable Digital Systems(5th year, Electrical Engineering curriculum) and ProcessorSynthesis and Modeling (5th year, Computer/Electricalengineering curriculum) disciplines.